It is oftentimes desirable to have synchronous transmission of digital signals from one node to another in a digital transmission system. However, synchronization errors occur when the average rate of digital bits received by a node is not exactly equal to the average rate of bits transmitted therefrom. Such synchronization errors are referred to as "slips" and attributed to the fact that when the input transmission rate exceeds the output rate, bits would be arbitrarily deleted or, on the other hand, when the input transmission rate is lower than the output rate, bits are repeated or inserted arbitrarily. To assure synchronization and avoid slips, the nodes are necessarily synchronized to a reference timing signal. To this end, each node includes a local timing generator, commonly known as a lock clock, which generates timing signals at a predetermined frequency. The local clock is adjusted to be in synchronization with the reference timing signal.
A prior art arrangement for realizing the desired synchronization is described in U.S. Pat. No. 4,305,045 issued Dec. 8, 1981 to Metz et al. Disclosed is a frequently estimating and synthesizing arrangement that includes a programmable controller as part of a single phase-locked-loop (PLL) to control digitally an oscillator for achieving the desired synchronization of the local clock. In such an arrangement, a particular one of transmission links to the node is fixedly connected to the PLL and provides thereto a bit stream on that particular link. This bit stream is used by the PLL to derive the reference timing signal for synchronization. However, a problem arises when this particular link fails. The digitally controlled oscillator is allowed to free-run (i.e. oscillate irrespective of any external control) at the long-term average frequency known at the node at the time of the failure. Consequently, the free-run stability of the digitally controlled oscillator is critically important in order to maintain performance objectives. Such stability is achieved by using a precision crystal oscillator kept at a temperature within a meticulously narrow range. This stability requirement undesirably incurs a substantial cost to the arrangement, stemming from the expensiveness of the oscillator used and the maintenance of the almost constant temperature environment.
An attempt has been made to solve the above-identified problem by using a digital synchronizer wherein the frequency estimating and frequency synthesizing functions are made separate. Such a digital synchronizer is described in U.S. Pat. No. 4,633,193, issued Dec. 30, 1986 to Scordo. The frequency estimation in this synchronizer is realized by computing an estimate of a difference in frequency between a received reference timing signal and a signal of a predetermined frequency, which is generated by a local fixed oscillator. A phase value representing this estimate is supplied to a phase-locked oscillator to control a digitally controlled oscillator for generating a signal having a frequency which equals the algebraic sum of the predetermined frequency and the compound frequency difference. In the event that the reference timing signal is lost or a phase error is too great, the last generated phase value is retained at a constant value and continuously supplied to the phase-locked oscillator. Consequently, even though the phase-locked oscillator is allowed to free-run, it yields an output with a stability equal to the fixed frequency oscillator, rather than the digitally controlled oscillator as required before. This reduces the aforementioned cost relating to the maintenance of the stability of the digitally controlled oscillator. Nevertheless, the cost of this digital synchronizer is still unreasonably high. This stems from the fact that the supporting circuitry of the synchronizer including the circuit for computing the phase value is undesirably complex. Moreover, the digital synchronizer also calls for a precision crystal oscillator which is expensive. The inclusion of such complex circuitry and expensive oscillator inevitably contributes to the high cost of the synchronizer.
Accordingly, it is desirable to have an apparatus which not only provides accurate synchronization, but is also inexpensive and simple in design.